/*
 * FH8856.h
 *
 *  Created on: Jun 20, 2016
 *      Author: duobao
 */

#ifndef FH8856V300_H_
#define FH8856V300_H_
#define GPIO0_REG_BASE          (0xf0300000)
#define GPIO1_REG_BASE          (0xf4000000)
#define I2C0_REG_BASE           (0xf0200000)
#define WDT_REG_BASE            (0xf0d00000)
#define SPI0_REG_BASE           (0xf0500000)
#define SPI1_REG_BASE           (0xf0600000)
#define UART0_REG_BASE          (0xf0700000)
#define UART1_REG_BASE          (0xf0800000)
#define RTC_REG_BASE            (0xf1500000)
#define SDC0_REG_BASE           (0xe2000000)
#define SDC1_REG_BASE           (0xe2200000)
#define AES_REG_BASE            (0xe8200000)
#define EFUSE_REG_BASE          (0xf1600000)
#define PMU_REG_BASE            (0xf0000000)
#define DMAC0_REG_BASE          (0xe0300000)
#define GMAC_REG_BASE           (0xE0600000)
#define REG_TIMER_BASE          (0xf0c00000)
#define HASH_REG_BASE           (0xf1d00000)

#define REG_EPHY_BASE          (0xf1c00000)
#define REG_MDIO_BASE          (REG_EPHY_BASE + 0x600)
#define UART_CLOCK_FREQ        (16666667)   //15MHZ

#define REG_PMU_CHIP_ID                  (PMU_REG_BASE + 0x0000)
#define REG_PMU_IP_VER                   (PMU_REG_BASE + 0x0004)
#define REG_PMU_FW_VER                   (PMU_REG_BASE + 0x0008)
#define REG_PMU_CLK_SEL                  (PMU_REG_BASE + 0x000c)
#define REG_PMU_SYS_CTRL                 (PMU_REG_BASE + 0x000c)
#define REG_PMU_PLL0                     (PMU_REG_BASE + 0x0010)
#define REG_PMU_PLL1                     (PMU_REG_BASE + 0x0014)
#define REG_PMU_PLL0_CTR                (PMU_REG_BASE + 0x0018)
#define REG_PMU_CLK_GATE                 (PMU_REG_BASE + 0x001c)
#define REG_PMU_CLK_GATE1                (PMU_REG_BASE + 0x0020)
#define REG_PMU_CLK_DIV0                 (PMU_REG_BASE + 0x0024)
#define REG_PMU_CLK_DIV1                 (PMU_REG_BASE + 0x0028)
#define REG_PMU_CLK_DIV2                 (PMU_REG_BASE + 0x002c)
#define REG_PMU_CLK_DIV3                 (PMU_REG_BASE + 0x0030)
#define REG_PMU_CLK_DIV4                 (PMU_REG_BASE + 0x0034)
#define REG_PMU_CLK_DIV5                 (PMU_REG_BASE + 0x0038)
#define REG_PMU_CLK_DIV6                 (PMU_REG_BASE + 0x003c)
#define REG_PMU_SWRST_MAIN_CTRL          (PMU_REG_BASE + 0x0040)
#define REG_PMU_SWRST_AXI_CTRL           (PMU_REG_BASE + 0x0044)
#define REG_PMU_SWRST_AHB_CTRL           (PMU_REG_BASE + 0x0048)
#define REG_PMU_SWRST_APB_CTRL           (PMU_REG_BASE + 0x004c)
#define REG_PMU_SPC_IO_STATUS            (PMU_REG_BASE + 0x0054)
#define REG_PMU_SPC_FUN                  (PMU_REG_BASE + 0x0058)
#define REG_PMU_CLK_DIV7                 (PMU_REG_BASE + 0x005c)
#define REG_PMU_CLK_DIV8                 (PMU_REG_BASE + 0x0060)
#define REG_PMU_PLL2                     (PMU_REG_BASE + 0x0064)
#define REG_PMU_PLL2_CTRL                (PMU_REG_BASE + 0x0068)
#define REG_PMU_PLL1_CTRL                (PMU_REG_BASE + 0x006c)
#define REG_PMU_PAD_POWER_SEL            (PMU_REG_BASE + 0x0074)
#define REG_PMU_SWRSTN_NSR                (PMU_REG_BASE + 0x0078)
#define REG_PMU_SWRSTN_NSR1               (PMU_REG_BASE + 0x007c)



#define REG_PMU_PAD_CIS_HSYNC_CFG        (PMU_REG_BASE + 0x0080)
#define REG_PMU_PAD_CIS_VSYNC_CFG        (PMU_REG_BASE + 0x0084)
#define REG_PMU_PAD_CIS_PCLK_CFG         (PMU_REG_BASE + 0x0088)
#define REG_PMU_PAD_CIS_D_0_CFG          (PMU_REG_BASE + 0x008c)
#define REG_PMU_PAD_CIS_D_1_CFG          (PMU_REG_BASE + 0x0090)
#define REG_PMU_PAD_CIS_D_2_CFG          (PMU_REG_BASE + 0x0094)
#define REG_PMU_PAD_CIS_D_3_CFG          (PMU_REG_BASE + 0x0098)
#define REG_PMU_PAD_CIS_D_4_CFG          (PMU_REG_BASE + 0x009c)
#define REG_PMU_PAD_CIS_D_5_CFG          (PMU_REG_BASE + 0x00a0)
#define REG_PMU_PAD_CIS_D_6_CFG          (PMU_REG_BASE + 0x00a4)
#define REG_PMU_PAD_CIS_D_7_CFG          (PMU_REG_BASE + 0x00a8)
#define REG_PMU_PAD_CIS_D_8_CFG          (PMU_REG_BASE + 0x00ac)
#define REG_PMU_PAD_CIS_D_9_CFG          (PMU_REG_BASE + 0x00b0)
#define REG_PMU_PAD_CIS_D_10_CFG         (PMU_REG_BASE + 0x00b4)
#define REG_PMU_PAD_CIS_D_11_CFG         (PMU_REG_BASE + 0x00b8)
#define REG_PMU_PAD_MAC_RMII_CLK_CFG     (PMU_REG_BASE + 0x00bc)
#define REG_PMU_PAD_MAC_REF_CLK_CFG      (PMU_REG_BASE + 0x00c0)
#define REG_PMU_PAD_MAC_MDC_CFG          (PMU_REG_BASE + 0x00c4)
#define REG_PMU_PAD_MAC_MDIO_CFG         (PMU_REG_BASE + 0x00c8)
#define REG_PMU_PAD_MAC_COL_MII_CFG      (PMU_REG_BASE + 0x00cc)
#define REG_PMU_PAD_MAC_CRS_MII_CFG      (PMU_REG_BASE + 0x00d0)
#define REG_PMU_PAD_MAC_RXCK_CFG         (PMU_REG_BASE + 0x00d4)
#define REG_PMU_PAD_MAC_RXD0_CFG         (PMU_REG_BASE + 0x00d8)
#define REG_PMU_PAD_MAC_RXD1_CFG         (PMU_REG_BASE + 0x00dc)
#define REG_PMU_PAD_MAC_RXD2_MII_CFG     (PMU_REG_BASE + 0x00e0)
#define REG_PMU_PAD_MAC_RXD3_MII_CFG     (PMU_REG_BASE + 0x00e4)
#define REG_PMU_PAD_MAC_RXDV_CFG         (PMU_REG_BASE + 0x00e8)
#define REG_PMU_PAD_MAC_TXCK_CFG         (PMU_REG_BASE + 0x00ec)
#define REG_PMU_PAD_MAC_TXD0_CFG         (PMU_REG_BASE + 0x00f0)
#define REG_PMU_PAD_MAC_TXD1_CFG         (PMU_REG_BASE + 0x00f4)
#define REG_PMU_PAD_MAC_TXD2_MII_CFG     (PMU_REG_BASE + 0x00f8)
#define REG_PMU_PAD_MAC_TXD3_MII_CFG     (PMU_REG_BASE + 0x00fc)
#define REG_PMU_PAD_MAC_TXEN_CFG         (PMU_REG_BASE + 0x0100)
#define REG_PMU_PAD_MAC_RXER_MII_CFG     (PMU_REG_BASE + 0x0104)
#define REG_PMU_PAD_MAC_TXER_MII_CFG     (PMU_REG_BASE + 0x0108)
#define REG_PMU_PAD_GPIO_0_CFG           (PMU_REG_BASE + 0x010c)
#define REG_PMU_PAD_GPIO_1_CFG           (PMU_REG_BASE + 0x0110)
#define REG_PMU_PAD_GPIO_2_CFG           (PMU_REG_BASE + 0x0114)
#define REG_PMU_PAD_GPIO_3_CFG           (PMU_REG_BASE + 0x0118)
#define REG_PMU_PAD_GPIO_4_CFG           (PMU_REG_BASE + 0x011c)
#define REG_PMU_PAD_GPIO_5_CFG           (PMU_REG_BASE + 0x0120)
#define REG_PMU_PAD_GPIO_6_CFG           (PMU_REG_BASE + 0x0124)
#define REG_PMU_PAD_GPIO_7_CFG           (PMU_REG_BASE + 0x0128)
#define REG_PMU_PAD_GPIO_8_CFG           (PMU_REG_BASE + 0x012c)
#define REG_PMU_PAD_GPIO_9_CFG           (PMU_REG_BASE + 0x0130)
#define REG_PMU_PAD_GPIO_10_CFG          (PMU_REG_BASE + 0x0134)
#define REG_PMU_PAD_GPIO_11_CFG          (PMU_REG_BASE + 0x0138)
#define REG_PMU_PAD_GPIO_12_CFG          (PMU_REG_BASE + 0x013c)
#define REG_PMU_PAD_GPIO_13_CFG          (PMU_REG_BASE + 0x0140)
#define REG_PMU_PAD_GPIO_14_CFG          (PMU_REG_BASE + 0x0144)
#define REG_PMU_PAD_UART_RX_CFG          (PMU_REG_BASE + 0x0148)
#define REG_PMU_PAD_UART_TX_CFG          (PMU_REG_BASE + 0x014c)
#define REG_PMU_PAD_CIS_SCL_CFG          (PMU_REG_BASE + 0x0150)
#define REG_PMU_PAD_CIS_SDA_CFG          (PMU_REG_BASE + 0x0154)
#define REG_PMU_PAD_I2C_SCL_CFG          (PMU_REG_BASE + 0x0158)
#define REG_PMU_PAD_I2C_SDA_CFG          (PMU_REG_BASE + 0x015c)
#define REG_PMU_PAD_SSI0_CLK_CFG         (PMU_REG_BASE + 0x0160)
#define REG_PMU_PAD_SSI0_TXD_CFG         (PMU_REG_BASE + 0x0164)
#define REG_PMU_PAD_SSI0_CSN_0_CFG       (PMU_REG_BASE + 0x0168)
#define REG_PMU_PAD_SSI0_CSN_1_CFG       (PMU_REG_BASE + 0x016c)
#define REG_PMU_PAD_SSI0_RXD_CFG         (PMU_REG_BASE + 0x0170)
#define REG_PMU_PAD_SD0_CD_CFG           (PMU_REG_BASE + 0x0174)
#define REG_PMU_PAD_SD0_WP_CFG           (PMU_REG_BASE + 0x0178)
#define REG_PMU_PAD_SD0_CLK_CFG          (PMU_REG_BASE + 0x017c)
#define REG_PMU_PAD_SD0_CMD_RSP_CFG      (PMU_REG_BASE + 0x0180)
#define REG_PMU_PAD_SD0_DATA_0_CFG       (PMU_REG_BASE + 0x0184)
#define REG_PMU_PAD_SD0_DATA_1_CFG       (PMU_REG_BASE + 0x0188)
#define REG_PMU_PAD_SD0_DATA_2_CFG       (PMU_REG_BASE + 0x018c)
#define REG_PMU_PAD_SD0_DATA_3_CFG       (PMU_REG_BASE + 0x0190)
#define REG_PMU_PAD_SD1_CD_CFG           (PMU_REG_BASE + 0x0194)
#define REG_PMU_PAD_SD1_WP_CFG           (PMU_REG_BASE + 0x0198)
#define REG_PMU_PAD_SD1_CLK_CFG          (PMU_REG_BASE + 0x019c)
#define REG_PMU_PAD_SD1_CMD_RSP_CFG      (PMU_REG_BASE + 0x01a0)
#define REG_PMU_PAD_SD1_DATA_0_CFG       (PMU_REG_BASE + 0x01a4)
#define REG_PMU_PAD_SD1_DATA_1_CFG       (PMU_REG_BASE + 0x01a8)
#define REG_PMU_PAD_SD1_DATA_2_CFG       (PMU_REG_BASE + 0x01ac)
#define REG_PMU_PAD_SD1_DATA_3_CFG       (PMU_REG_BASE + 0x01b0)
#define REG_PMU_ARM_INT_0                (PMU_REG_BASE + 0x01e0)
#define REG_PMU_ARM_INT_1                (PMU_REG_BASE + 0x01e4)
#define REG_PMU_ARM_INT_2                (PMU_REG_BASE + 0x01e8)
#define REG_PMU_A625_INT_0               (PMU_REG_BASE + 0x01ec)
#define REG_PMU_A625_INT_1               (PMU_REG_BASE + 0x01f0)
#define REG_PMU_A625_INT_2               (PMU_REG_BASE + 0x01f4)
#define REG_PMU_DMA                      (PMU_REG_BASE + 0x01f8)
#define REG_PMU_WDT_CTRL                 (PMU_REG_BASE + 0x01fc)
#define REG_PMU_DBG_STAT0                (PMU_REG_BASE + 0x0200)
#define REG_PMU_DBG_STAT1                (PMU_REG_BASE + 0x0204)
#define REG_PMU_USB_CFG                  (PMU_REG_BASE + 0x0214)
#define REG_PMU_USB_SYS0                 (PMU_REG_BASE + 0x0210)
#define REG_PMU_USB_SYS1                 (PMU_REG_BASE + 0x0228)
#define REG_PMU_USB_TUNE                 (PMU_REG_BASE + 0x0218)
#define REG_PMU_BOOT_MODE                (PMU_REG_BASE + 0x0330)
#define REG_PMU_DDR_SIZE                 (PMU_REG_BASE + 0x0334)
#define REG_PMU_CHIP_INFO                (PMU_REG_BASE + 0x033c)
#define REG_PMU_EPHY_PARAM               (PMU_REG_BASE + 0x0340)
#define REG_PMU_RTC_PARAM                (PMU_REG_BASE + 0x0344)
#define REG_PMU_SD1_FUNC_SEL             (PMU_REG_BASE + 0x03a0)
#define REG_PMU_A625BOOT0                (PMU_REG_BASE + 0x2000)
#define REG_PMU_A625BOOT1                (PMU_REG_BASE + 0x2004)
#define REG_PMU_A625BOOT2                (PMU_REG_BASE + 0x2008)
#define REG_PMU_A625BOOT3                (PMU_REG_BASE + 0x200c)
#define REG_PMU_A625_START_CTRL          (PMU_REG_BASE + 0x2010)
#define REG_PMU_ARC_INTC_MASK            (PMU_REG_BASE + 0x2014)
#define REG_PMU_EFHY_REG0                (PMU_REG_BASE + 0x2108)
#define REG_PMU_EFHY_REG1                (PMU_REG_BASE + 0x210c)
#define REG_PMU_SCU_PLL_WREN             (PMU_REG_BASE + 0x2110)



#define REG_PMU_CLK_GATE0 (REG_PMU_CLK_GATE)

/* mac phy clk below */
#define CLK_SCAN_BIT_POS                (28)
#define INSIDE_PHY_ENABLE_BIT_POS       (24)
#define MAC_REF_CLK_DIV_MASK            (0x0f)
#define MAC_REF_CLK_DIV_BIT_POS         (24)
#define MAC_PAD_RMII_CLK_MASK           (0x0f)
#define MAC_PAD_RMII_CLK_BIT_POS        (24)
#define MAC_PAD_MAC_REF_CLK_BIT_POS     (28)
#define ETH_REF_CLK_OUT_GATE_BIT_POS    (25)
#define ETH_RMII_CLK_OUT_GATE_BIT_POS   (28)
#define IN_OR_OUT_PHY_SEL_BIT_POS       (28)
#define INSIDE_CLK_GATE_BIT_POS         (0)
#define INSIDE_PHY_SHUTDOWN_BIT_POS     (31)
#define INSIDE_PHY_RST_BIT_POS          (30)
#define INSIDE_PHY_TRAINING_BIT_POS     (27)
#define INSIDE_PHY_TRAINING_MASK        (0x0f)

enum DMA_HW_HS_MAP
{
    ACODEC_RX = 0,
    ACODEC_TX,
    SPI1_RX,
    SPI1_TX,
    SPI0_RX,
    SPI0_TX,
    UART0_RX,
    UART0_TX,
    UART1_RX,
    UART1_TX,
    I2S_RX,
    I2S_TX,
    UART2_RX,
    UART2_TX,
    SPI2_RX,
    SPI2_TX,
    DMA_HW_HS_END,
};


struct s_train_val{
	unsigned char *name;
	unsigned int src_add;
	unsigned int src_mask;
	unsigned int src_vaild_index;
	unsigned char *dst_base_name;
	unsigned int dst_add;
	unsigned int dst_vaild_index;
	unsigned int *bind_train_array;
	unsigned int bind_train_size;
	int usr_train_offset;
};

struct gmac_plat_info{
	unsigned int regs;
	unsigned int id;
#define MAX_PHY_DRIVER_SUPPORT_SIZE	5
	char *phy_driver_list[MAX_PHY_DRIVER_SUPPORT_SIZE];
    void *p_cfg_array;
};

#define FH_GMAC_PHY_IP101G	0x02430C54
#define FH_GMAC_PHY_RTL8201	0x001CC816
#define FH_GMAC_PHY_TI83848	0xFFFFFFFF
#define FH_GMAC_PHY_INTERNAL 0x441400
#define FH_GMAC_PHY_INTERNAL_V2 0x46480000
#define FH_GMAC_PHY_RTL8211F 0x001cc916
#define FH_GMAC_PHY_MAE0621 0x7b744411
#define FH_GMAC_PHY_JL2101 0x937c4032
#define FH_GMAC_PHY_DUMMY	0xE3FFE3FF

#endif /* FH8856V300_H_ */
